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Run-time power and performance scaling in 28 nm FPGAs

Research output: Contribution to journalArticle

Original languageEnglish
JournalIET Computers and Digital Techniques
Volume8
Issue number4
DOIs
DatePublished - Jul 2014

Abstract

The ability of scaling power and performance at run-time enables the creation of computing systems in which energy is consumed in proportion of the work to be done and the time available to do it. These systems favour active energy-efficient states in which useful computation is performed at low energy instead of using inactive energy savings modes that incur large latency and energy penalties to enter and exit modes in which the system is halted. This is particular useful in servers that spend most of their time at around 30% utilization and are rarely fully idle or at maximum utilization. A feature of an energy proportional computing system is that it must exhibit a wide dynamic range with multiple levels of energy and performance available. In this context this paper investigates how these levels can be obtained in commercially available state-of-the-art 28 nm FPGAs and characterizes its benefits. Adaptive voltage and frequency scaling is employed to deliver proportional performance and power in these FPGA devices. The results reveal that the available voltage and frequency margins create a large number of performance and energy states with scaling possible at run-time with low overheads. Power savings of up to 64.98% are possible maintaining the original performance at a lower voltage.

    Research areas

  • low power, high performance

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    Rights statement: This paper is a postprint of a paper submitted to and accepted for publication in IET Computers & Digital Techniques and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library

    Accepted author manuscript, 467 KB, PDF document

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