Scalability of network-on-chip communication architecture for 3-D meshes

I D B Pamunuwa, A. Weldezion, H Tenhunen, M Grange, A Jantsch, R. Weerasekera, Zhonghai Lu

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

47 Citations (Scopus)

Abstract

Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3D network-on-chips (NoC) using through-silicon-vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3D NoC is examined under both communication architectures and compared to 2D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.
Original languageEnglish
Title of host publicationACM/IEEE International Symposium on Networks-on-Chip
Place of PublicationSan Diego, CA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages114-123
Number of pages10
ISBN (Electronic)978-1-4244-4143-3
ISBN (Print)978-1-4244-4142-6
DOIs
Publication statusPublished - 12 Jun 2009

Fingerprint Dive into the research topics of 'Scalability of network-on-chip communication architecture for 3-D meshes'. Together they form a unique fingerprint.

Cite this