Abstract
Design constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3D network-on-chips (NoC) using through-silicon-vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3D NoC is examined under both communication architectures and compared to 2D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.
Original language | English |
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Title of host publication | 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip |
Place of Publication | San Diego, CA |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 114-123 |
Number of pages | 10 |
ISBN (Electronic) | 978-1-4244-4143-3 |
ISBN (Print) | 978-1-4244-4142-6 |
DOIs | |
Publication status | Published - 12 Jun 2009 |
Research Groups and Themes
- Photonics and Quantum