Abstract
We investigate two scalar coprocessors for accelerating the ITU-T G723.1 and G729A speech coders. Architecture space exploration indicates up to 72% reduction in the total number of instructions executed through the introduction of custom instructions and small changes to the C reference code. The accelerators are designed to be attached to a configurable embedded RISC CPU where they make use of the host register file and load/store infrastructure.
| Translated title of the contribution | Scalar coprocessors for accelerating the G723.1 and G729A speech coders |
|---|---|
| Original language | English |
| Article number | Issue 3 |
| Pages (from-to) | 703 - 710 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Consumer Electronics |
| Volume | 49 |
| DOIs | |
| Publication status | Published - Aug 2003 |
Bibliographical note
Publisher: Institute of Electrical and Electronics Engineers (IEEE)Fingerprint
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