Scheduling thread upon ready signal set when port transfers data on trigger time activation

David May (Inventor), Peter Hedinger (Inventor), Alastair Dixon (Inventor)

Research output: Patent

Abstract

A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said threads for execution in dependence on the ready signal.
Original languageEnglish
Patent numberUS7617386
IPCG06F 13/00
Publication statusPublished - 10 Nov 2009

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