In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.
|Translated title of the contribution||Self-timed architecture for masked successive approximation analog-to-digital conversion|
|Pages (from-to)||1 - 14|
|Number of pages||14|
|Journal||Journal of Circuits, Systems and Computers|
|Publication status||Published - Feb 2007|