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Masking is a well loved and widely deployed countermeasure against side channel attacks, in particular in software. Under certain assumptions (w.r.t. independence and noise level), masking provably prevents attacks up to a certain security order and leads to a predictable increase in the number of required leakages for successful attacks beyond this order. The noise level in typical processors where software masking is used may not be very high, thus low masking orders are not sufficient for real world security. Higher order masking however comes at a great cost, and therefore a number techniques have been published over the years that make such implementations more efficient via parallelisation in the form of bit or share slicing. We take two highly regarded schemes (ISW and Barthe et al.), and some corresponding open source implementations that make use of share slicing, and discuss their true security on an ARM Cortex-M0 and an ARM Cortex-M3 processor (both from the LPC series). We show that micro-architectural features ofthe M0 and M3 undermine the independence assumptions made in masking proofs and thus their theoretical guarantees do not translate into practice (even worse it seems unpredictable at which order leaks can be expected). Our results demonstrate how difficult it is to link theoretical security proofs to practical real-world security guarantees.
|Journal||IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES)|
|Publication status||Published - 19 Nov 2019|
Bibliographical noteThe acceptance date for this record is provisional and based upon the month of publication for the article.
Gao, S., Marshall, B., Page, D., & Oswald, M. E. (2019). Share-slicing: Friend or Foe? IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2020(1), 152-174. https://doi.org/10.13154/tches.v2020.i1.152-174