SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream

Simon N McIntosh-Smith (Inventor), John Rhoades (Inventor), Ken Cameron (Inventor), Paul Winser (Inventor), Ray McConnell (Inventor), Gajinder Panesar (Inventor)

Research output: Patent

Abstract

A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
Original languageEnglish
Patent number8127112
Publication statusPublished - 28 Feb 2012

Bibliographical note

This patent is based on the many-core computer architecture I developed while Vice President of Architecture at ClearSpeed Technology.

It describes fundamental new computer architecture techniques for applying data-parallel processing approaches to internet packet processing, a task which had previously been impossible to accomplish using a single instruction, multiple data (SIMD) architecture.

These new techniques delivered several significant steps forward over the state of the art, in terms of both performance and energy efficiency.

The new techniques also delivered a breakthrough in performance predictability (all packets would now take the same length of time to process, improving traffic management), and silicon area efficiency (a SIMD architecture is more efficient to implement as it removes the need for multiple instruction fetch, decode and issue units). Additionally this approach provided a number of processing elements, or PEs, proportional with the length of a packet, i.e. longer packets have more PEs to work on them. This in turn enabled scalable deep packet processing techniques for the first time.

This fundamental patent became very valuable, and was acquired from ClearSpeed Technology by one of the most successful microelectronics intellectual property companies, Rambus Inc. (Sunnyvale, CA), in a deal totalling $2 million USD.

This technology has subsequently led to a deal with US defence contractor Northrop Grumman worth over £100 million USD to ClearSpeed. The architecture we developed, and which is the subject of this patent, is now shipping in space and high altitude applications, due to its very high DSP performance at very low power and thermal dissipation.

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