Simultaneous multiprocessing in a software-defined heterogeneous FPGA

Jose Nunez-Yanez, Sam Amiri*, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Dario Suarez, Ruben Gran

*Corresponding author for this work

Research output: Contribution to journalArticle (Academic Journal)

5 Citations (Scopus)
232 Downloads (Pure)

Abstract

Heterogeneous chips that combine CPUs and FPGAs can distribute processing so that the algorithm tasks are mapped onto the most suitable processing element. New software-defined high-level design environments for these chips use general purpose languages such as C++ and OpenCL for hardware and interface generation without the need for register transfer language expertise. These advances in hardware compilers have resulted in significant increases in FPGA design productivity. In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the utilization of all the available CPU cores in parallel with the FPGA hardware accelerators. Instead of selecting the best processing element for a task and simply offloading onto it, we introduce two schedulers, Dynamic and LogFit, which distribute the tasks among all the resources in an optimal manner. A new platform is created based on interrupts that removes spin-locks and allows the processing cores to sleep when not performing useful work. For a compute-intensive application, we obtained up to 45.56% more throughput and 17.89% less energy consumption when all devices of a Zynq-7000 SoC collaborate in the computation compared against FPGA-only execution.

Original languageEnglish
Number of pages18
JournalJournal of Supercomputing
Early online date16 Apr 2018
DOIs
Publication statusE-pub ahead of print - 16 Apr 2018

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    Nunez-Yanez, J., Amiri, S., Hosseinabady, M., Rodríguez, A., Asenjo, R., Navarro, A., Suarez, D., & Gran, R. (2018). Simultaneous multiprocessing in a software-defined heterogeneous FPGA. Journal of Supercomputing. https://doi.org/10.1007/s11227-018-2367-9