Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip

Jose Nunez-Yanez, Mohammad Hosseinabady, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Rubén Gran-Tejero, Darió Suárez-Gracia

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

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Abstract

In this paper, we investigate how to enhance an existing software-defined framework to reduce overheads and enable the parallel utilization of all the programmable processing resources present in systems that include FPGA-based hardware accelerators. To remove overheads, a new hardware platform is created based on interrupts, which removes spin-locks and frees the processing resources. Additionally, instead of simply using the hardware accelerator to offload a task from the CPU, we propose a scheduler that dynamically distributes the tasks among all the resources to minimize load unbalance. The experimental evaluation shows that the interrupt-based heterogeneous platform increases performance by up 22% while reducing energy requirements by 15%. Additionally, we measure between 50% to 25% reduction in execution time when the CPU cores assist FPGA execution at the same level of energy requirements depending on hardware speed-ups.

Original languageEnglish
Title of host publicationParallel Computing is Everywhere
PublisherIOS Press
Pages677-686
Number of pages10
ISBN (Electronic)9781614998433
ISBN (Print)9781614998426
DOIs
Publication statusPublished - 7 Mar 2018

Publication series

NameAdvances in Parallel Computing
Volume32
ISSN (Print)0927-5452
ISSN (Electronic)1879-808X

Keywords

  • dynamic scheduler
  • energy reduction
  • FPGAs
  • heterogeneous
  • interrupts
  • performance improvement

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