We introduce the Skip-link architecture that dynam- ically reconfigures Network-on-Chip (NoC) topologies, in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip- links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in the literature such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. Our architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. Our technique does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. We evaluate the performance using a cycle-accurate simulation with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating hop count and energy reductions of around 10%.
|Translated title of the contribution||Skip-links: A Dynamically Reconfiguring Topology for Energy-efficient NoCs|
|Title of host publication||International Symposium on System-on-Chip 2010|
|Publication status||Published - Sep 2010|