Abstract
In this paper, we investigate how the need for static analysis of data flowing
through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow
network optimisations to improve runtime behaviour. Our approach is to replace a priori
static analysis with run-time optimisations, taking place in the network itself. To do this, we
introduce our selfoptimising NoC topology: Skip-links, which inserts long-range links into a
standard mesh.
through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow
network optimisations to improve runtime behaviour. Our approach is to replace a priori
static analysis with run-time optimisations, taking place in the network itself. To do this, we
introduce our selfoptimising NoC topology: Skip-links, which inserts long-range links into a
standard mesh.
| Original language | English |
|---|---|
| Title of host publication | Electronic System Design (ISED), 2010 International Symposium on |
| Pages | 14-19 |
| Publication status | Published - 20 Dec 2010 |