In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our self- optimising NoC topology: Skip-links, which inserts long-range links into a standard mesh. We evaluate the performance of Skip-links at run-time against the optimal configuration, as determined by static analysis, for both the transpose and tornado traffic patterns. We show that the local decision-making algorithm employed by Skip-links comes close to optimum, carrying 70% of theoretical maximum traffic flows for tornado traffic, and reducing average hop counts by 18% for transpose traffic.
|Translated title of the contribution||Skip the Analysis: Self-optimising Networks-on-Chip (Invited paper)|
|Title of host publication||International Symposium on Electronic System Design (ISED)|
|Publication status||Published - Dec 2010|
Bibliographical noteConference Proceedings/Title of Journal: Proc. International Symposium on Electronic System Design (ISED)
Conference Organiser: IEEE
Hollis, SJ., & Jackson, CR. (2010). Skip the Analysis: Self-optimising Networks-on-Chip (Invited paper). In International Symposium on Electronic System Design (ISED) http://www.cs.bris.ac.uk/home/simon/papers/Hollis-Skip_The_Analysis-ISED2010.pdf