SNDR sensitivity analysis for cascaded ΣΔ modulators

J Morizio, M Hoke, T Kocak, C Geddie

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

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Abstract

Cascade, single and multi-bit, ΣΔ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded ΣΔ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded ΣΔ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized
Translated title of the contributionSNDR sensitivity analysis for cascaded sigma-delta modulators
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, Geneva
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages765 - 762
Volume3
ISBN (Print)0780354826
DOIs
Publication statusPublished - 28 May 2000
EventInternational Symposium on Circuits and Systems - Geneva, Switzerland
Duration: 1 May 2000 → …

Conference

ConferenceInternational Symposium on Circuits and Systems
CountrySwitzerland
CityGeneva
Period1/05/00 → …

Bibliographical note

Conference Proceedings/Title of Journal: IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century
Conference Organiser: IEEE
Rose publication type: Conference contribution

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Keywords

  • cascade networks
  • integrating circuits
  • network parameters
  • sigma-delta modulation

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