SNDR sensitivity analysis for cascaded ΣΔ modulators

J Morizio; M Hoke; T Kocak; C Geddie

doi:10.1109/ISCAS.2000.856172

SNDR sensitivity analysis for cascaded ΣΔ modulators

J Morizio, M Hoke, T Kocak, C Geddie

Department of Electrical & Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

259 Downloads (Pure)

Abstract

Cascade, single and multi-bit, ΣΔ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded ΣΔ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded ΣΔ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized

Translated title of the contribution	SNDR sensitivity analysis for cascaded sigma-delta modulators
Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, Geneva
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	765 - 762
Volume	3
ISBN (Print)	0780354826
DOIs	https://doi.org/10.1109/ISCAS.2000.856172
Publication status	Published - 28 May 2000
Event	International Symposium on Circuits and Systems - Geneva, Switzerland Duration: 1 May 2000 → …

Conference

Conference	International Symposium on Circuits and Systems
Country	Switzerland
City	Geneva
Period	1/05/00 → …

Bibliographical note

Conference Proceedings/Title of Journal: IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century
Conference Organiser: IEEE
Rose publication type: Conference contribution

Terms of use: Copyright © 2000 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems, 2000 (ISCAS 2000). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org.

By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

Keywords

cascade networks
integrating circuits
network parameters
sigma-delta modulation

Access to Document

10.1109/ISCAS.2000.856172

Morizio ISCAS 2000Accepted author manuscript, 323 KB

http://hdl.handle.net/1983/1041

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abstract = "Cascade, single and multi-bit, ΣΔ architectures provide stable, high order quantization noise shaping used in high resolution A/D conversion. One major disadvantage of cascaded ΣΔ topologies is the extreme SNDR sensitivity to gain mismatch between the analog modulator and the digital error correction logic. This paper will investigate this SNDR sensitivity phenomenon for a 6th order, 1-bit quantizer and 4th order, 5-bit quantizer cascaded ΣΔ A/D system. Circuit parameters of the switched capacitor integrator such as amplifier open loop gain, integrator gain, and amplifier offsets and layout parasitics are characterized",

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Morizio, J, Hoke, M, Kocak, T & Geddie, C 2000, SNDR sensitivity analysis for cascaded ΣΔ modulators. in IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, Geneva. vol. 3, Institute of Electrical and Electronics Engineers (IEEE), pp. 765 - 762, International Symposium on Circuits and Systems, Geneva, Switzerland, 1/05/00. https://doi.org/10.1109/ISCAS.2000.856172

SNDR sensitivity analysis for cascaded ΣΔ modulators. / Morizio, J; Hoke, M; Kocak, T; Geddie, C.

IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century, Geneva. Vol. 3 Institute of Electrical and Electronics Engineers (IEEE), 2000. p. 765 - 762.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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