STEP: A Unified Design Methodology for Secure Test and IP Core Protection

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Original language	English
Title of host publication	Great Lakes Symposium on VLSI (GLSVLSI)
Publisher	Association for Computing Machinery
Pages	333–338
Publication status	Published - May 2012

Handle.net

@inproceedings{490bb95fbc034f85b9d7ef28c34bfdf1,

title = "STEP: A Unified Design Methodology for Secure Test and IP Core Protection",

author = "P. Yeolekar and Shafik, \{Rishad A\} and Jimson Mathew and Pradhan, \{Dhiraj K\} and Mohanty, \{S. P.\}",

year = "2012",

month = may,

language = "English",

pages = "333–338",

booktitle = "Great Lakes Symposium on VLSI (GLSVLSI)",

publisher = "Association for Computing Machinery",

address = "United States",

}

TY - GEN

T1 - STEP: A Unified Design Methodology for Secure Test and IP Core Protection

AU - Yeolekar, P.

AU - Shafik, Rishad A

AU - Mathew, Jimson

AU - Pradhan, Dhiraj K

AU - Mohanty, S. P.

PY - 2012/5

Y1 - 2012/5

M3 - Conference Contribution (Conference Proceeding)

SP - 333

EP - 338

BT - Great Lakes Symposium on VLSI (GLSVLSI)

PB - Association for Computing Machinery

ER -