Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources

Qianqiao Chen, Vaibhawa Mishra, Jose Nunez-Yanez, Georgios Zervas

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)

Abstract

With the evolution of cloud computing, FPGAs are involved in the data centers thanks to their high performance and logic reconfigurable features. To efficiently make use of data center resources, recent rack scale architecture tends to disaggregate data center resources. This paper proposes the Synchronizing Network wide Function Reconfiguration (SNFR) protocol that aims to synchronize the reconfiguration of coherent functions on disaggregated FPGA resources deployed across the network. The associated protocol processor is implemented. The synchronized reconfiguration is captured by the Xilinx debug core and network traffic analyzer. The experimental section shows that the protocol processor can support maximum 9 Gbps traffic and introduces additional latency ranged from from 0.1 μs to 0.21μs.

Original languageEnglish
Title of host publication2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1-6
Number of pages6
Volume2018-January
ISBN (Electronic)9781538637975
DOIs
Publication statusPublished - 2 Feb 2018
Event2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 - Cancun, Mexico
Duration: 4 Dec 20176 Dec 2017

Conference

Conference2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017
CountryMexico
CityCancun
Period4/12/176/12/17

Fingerprint Dive into the research topics of 'Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources'. Together they form a unique fingerprint.

Cite this