Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources

Qianqiao Chen; Vaibhawa Mishra; Jose Nunez-Yanez; Georgios Zervas

doi:10.1109/RECONFIG.2017.8279822

Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources

Qianqiao Chen, Vaibhawa Mishra, Jose Nunez-Yanez, Georgios Zervas

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

With the evolution of cloud computing, FPGAs are involved in the data centers thanks to their high performance and logic reconfigurable features. To efficiently make use of data center resources, recent rack scale architecture tends to disaggregate data center resources. This paper proposes the Synchronizing Network wide Function Reconfiguration (SNFR) protocol that aims to synchronize the reconfiguration of coherent functions on disaggregated FPGA resources deployed across the network. The associated protocol processor is implemented. The synchronized reconfiguration is captured by the Xilinx debug core and network traffic analyzer. The experimental section shows that the protocol processor can support maximum 9 Gbps traffic and introduces additional latency ranged from from 0.1 μs to 0.21μs.

Original language	English
Title of host publication	2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1-6
Number of pages	6
Volume	2018-January
ISBN (Electronic)	9781538637975
DOIs	https://doi.org/10.1109/RECONFIG.2017.8279822
Publication status	Published - 2 Feb 2018
Event	2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 - Cancun, Mexico Duration: 4 Dec 2017 → 6 Dec 2017

Conference

Conference	2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017
Country/Territory	Mexico
City	Cancun
Period	4/12/17 → 6/12/17

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10.1109/RECONFIG.2017.8279822

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@inproceedings{03ff893643cc4b0a8258422d644026df,

title = "Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources",

abstract = "With the evolution of cloud computing, FPGAs are involved in the data centers thanks to their high performance and logic reconfigurable features. To efficiently make use of data center resources, recent rack scale architecture tends to disaggregate data center resources. This paper proposes the Synchronizing Network wide Function Reconfiguration (SNFR) protocol that aims to synchronize the reconfiguration of coherent functions on disaggregated FPGA resources deployed across the network. The associated protocol processor is implemented. The synchronized reconfiguration is captured by the Xilinx debug core and network traffic analyzer. The experimental section shows that the protocol processor can support maximum 9 Gbps traffic and introduces additional latency ranged from from 0.1 μs to 0.21μs.",

author = "Qianqiao Chen and Vaibhawa Mishra and Jose Nunez-Yanez and Georgios Zervas",

year = "2018",

month = feb,

day = "2",

doi = "10.1109/RECONFIG.2017.8279822",

language = "English",

volume = "2018-January",

pages = "1--6",

booktitle = "2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

note = "2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 ; Conference date: 04-12-2017 Through 06-12-2017",

}

Chen, Q, Mishra, V, Nunez-Yanez, J & Zervas, G 2018, Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. in 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. vol. 2018-January, Institute of Electrical and Electronics Engineers (IEEE), pp. 1-6, 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, 4/12/17. https://doi.org/10.1109/RECONFIG.2017.8279822

Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources. / Chen, Qianqiao; Mishra, Vaibhawa; Nunez-Yanez, Jose et al.
2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017. Vol. 2018-January Institute of Electrical and Electronics Engineers (IEEE), 2018. p. 1-6.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources

AU - Chen, Qianqiao

AU - Mishra, Vaibhawa

AU - Nunez-Yanez, Jose

AU - Zervas, Georgios

PY - 2018/2/2

Y1 - 2018/2/2

N2 - With the evolution of cloud computing, FPGAs are involved in the data centers thanks to their high performance and logic reconfigurable features. To efficiently make use of data center resources, recent rack scale architecture tends to disaggregate data center resources. This paper proposes the Synchronizing Network wide Function Reconfiguration (SNFR) protocol that aims to synchronize the reconfiguration of coherent functions on disaggregated FPGA resources deployed across the network. The associated protocol processor is implemented. The synchronized reconfiguration is captured by the Xilinx debug core and network traffic analyzer. The experimental section shows that the protocol processor can support maximum 9 Gbps traffic and introduces additional latency ranged from from 0.1 μs to 0.21μs.

AB - With the evolution of cloud computing, FPGAs are involved in the data centers thanks to their high performance and logic reconfigurable features. To efficiently make use of data center resources, recent rack scale architecture tends to disaggregate data center resources. This paper proposes the Synchronizing Network wide Function Reconfiguration (SNFR) protocol that aims to synchronize the reconfiguration of coherent functions on disaggregated FPGA resources deployed across the network. The associated protocol processor is implemented. The synchronized reconfiguration is captured by the Xilinx debug core and network traffic analyzer. The experimental section shows that the protocol processor can support maximum 9 Gbps traffic and introduces additional latency ranged from from 0.1 μs to 0.21μs.

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DO - 10.1109/RECONFIG.2017.8279822

M3 - Conference Contribution (Conference Proceeding)

AN - SCOPUS:85046962081

VL - 2018-January

SP - 1

EP - 6

BT - 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017

Y2 - 4 December 2017 through 6 December 2017

ER -

Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources

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ENergy Efficient Adaptive Computing with multi-grain heterogeneous architectures (ENEAC)

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Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources

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ENergy Efficient Adaptive Computing with multi-grain heterogeneous architectures (ENEAC)

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