Test Generation in Systolic Architecture for Multiplication over GF(2^m)

Research output: Contribution to journal › Article (Academic Journal) › peer-review

Translated title of the contribution	Test Generation in Systolic Architecture for Multiplication over GF(2^m)
Original language	English
Article number	-
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Publication status	Published - 2009

Other identifier: 2001044

Access to Document

@article{3bad5bbe594d4c089e01d87b128706f8,

title = "Test Generation in Systolic Architecture for Multiplication over GF(2\textasciicircum{}m)",

author = "H. Rahaman and Jimson Mathew and Pradhan Dhiraj",

note = "Other identifier: 2001044",

year = "2009",

language = "English",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1557-9999",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

}

TY - JOUR

T1 - Test Generation in Systolic Architecture for Multiplication over GF(2^m)

AU - Rahaman, H.

AU - Mathew, Jimson

AU - Dhiraj, Pradhan

N1 - Other identifier: 2001044

PY - 2009

Y1 - 2009

M3 - Article (Academic Journal)

SN - 1557-9999

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

M1 - -

ER -