Test scheduling for network-on-chip with BIST and precedence constraints

Liu Chunsheng, E Cota, H Sharif, DK Pradhan

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

46 Citations (Scopus)

Abstract

Network-on-a-chip (NoC) is becoming a promising paradigm of core-based system. We propose a new method for test scheduling in NoC. The method is based on the use of a dedicated routing path for the test of each core. We show that test scheduling under this approach is NP-complete and present an ILP model for solving small NoC instances. For NoCs with larger number of cores, we present an efficient heuristic. We then improve the heuristic by including BISTs and precedence constraints. Experimental results for the ITC'02 SoC benchmarks show that the new method leads to substantial reduction on test application time compared to previous work. The inclusion of BIST tests and precedence constraints provides a comprehensive solution for test scheduling in NoC.
Translated title of the contributionTest scheduling for network-on-chip with BIST and precedence constraints
Original languageEnglish
Title of host publicationUnknown
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1369 - 1378
Number of pages9
Publication statusPublished - Nov 2004

Bibliographical note

Conference Proceedings/Title of Journal: International Test Conference, 2004. Proceedings.

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