Abstract
Multi-threaded processor architectures are capable of concurrently executing multiple threads using a shared execution resource. Two of their advantages are their ability to hide latency within a thread, and their high execution efficiency. Unfortunately, single thread performance is often poor. In this paper we present a simple model of a multi-threaded processor, and show how an t occam-like language may be compiled into fine grained threads suitable for executing on this processor. These fine grained threads allow all but the most serial programs to be compiled into multiple threads. Thus, poor single thread performance is avoided by ensuring that sufficient threads are always available, even at the instruction level. We call this technique `uniform heterogeneous multi-threading' (UHM). A compiler implementing UHM has been built, along with a cycle accurate simulator of a UHM processor. We demonstrate that the processor is capable of good performance, whilst being simple to design and build.
Translated title of the contribution | The 'Uniform Heterogeneous Multi-threaded' Processor Architecture |
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Original language | English |
Title of host publication | Communicating Process Architectures 2001 |
Publisher | IOS Press |
Pages | 103 - 116 |
Number of pages | 13 |
ISBN (Print) | 9781586032029 |
Publication status | Published - Sept 2001 |
Publication series
Name | Concurrent Systems Engineering Series |
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Volume | 59 |
ISSN (Print) | 1383-7575 |
Bibliographical note
Editors: Alan Chalmers, Majid Mirmehdi and Henk MullerISBN: 158603202X
Publisher: IOS Press
Name and Venue of Conference: Communicating Process Architectures 2001, World Occam and Transputer Group WoTUG-24, Bristol, September