The XMOS Architecture and XS1 Chips

David May

Research output: Contribution to journalArticle (Academic Journal)peer-review

11 Citations (Scopus)

Abstract

The XMOS architecture scales from real-time systems with a single multithreaded processor to systems with thousands of processors. Concurrent processing, communications and I/O are supported by the instruction set of the XCore processors and by the message-routing techniques and protocols in the XMOS interconnect. The event-driven architecture supports energy-efficient multicore and multichip systems in which cores are active only when needed.
Original languageEnglish
Number of pages11
JournalIEEE Micro
Volume32
Issue number6
Publication statusAccepted/In press - 2012

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