Thermal transport in Superlattice Castellated Field Effect Transistors

Callum Middleton, Stefano Dalcanale, Michael Uren, James Pomeroy, Michael J Uren, Josephine Chang, Justine Parke, Ishan Wathuthanthri, Ken Nagamatsu, Salat Salaru, Martin Kuball

Research output: Contribution to journalArticle (Academic Journal)

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Abstract

Heat extraction from novel GaN/AlGaN superlattice castellated field effect transistors developed as an RF switch is studied. The device thermal resistance was determined as 19.1 ± 0.7 K/(W/mm) from a combination of Raman thermography
measurements, and gate resistance thermometry. Finite element simulations were used to predict the peak temperatures and show that the three-dimensional gate structure aids the extraction of heat generated in the channel. The calculated heat flux in the castellations shows that the gate metal provides a high thermal conductivity path, bypassing the lower thermal conductivity superlattice, reducing channel temperatures by as much as 23%.
Original languageEnglish
Pages (from-to)1374-1377
Number of pages4
JournalIEEE Electron Device Letters
Volume40
Issue number9
DOIs
Publication statusPublished - 18 Jul 2019

Structured keywords

  • CDTR

Keywords

  • Logic gates
  • Temperature measurement
  • Heating systems
  • Thermal resistance
  • Thermal conductivity
  • Superlattices

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  • Projects

    ECCI proposal

    Kuball, M. H. H.

    1/06/1730/11/20

    Project: Research

    Cite this

    Middleton, C., Dalcanale, S., Uren, M., Pomeroy, J., Uren, M. J., Chang, J., Parke, J., Wathuthanthri, I., Nagamatsu, K., Salaru, S., & Kuball, M. (2019). Thermal transport in Superlattice Castellated Field Effect Transistors. IEEE Electron Device Letters, 40(9), 1374-1377. https://doi.org/10.1109/LED.2019.2929424