Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress

Juefei Yang; Saeed Jahdi; Bernard Stark; Phil Mellor; Ruizhu Wu; Jose Ortiz-Gonzalez; Olayiwola Alatise

doi:10.30420/565822148

Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress

Juefei Yang^*, Saeed Jahdi^*, Bernard Stark, Phil Mellor, Ruizhu Wu, Jose Ortiz-Gonzalez, Olayiwola Alatise

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

1 Citation (Scopus)

53 Downloads (Pure)

Abstract

In this paper, long-period positive and negative DC gate bias stressing is applied on the SiC symmetrical and asymmetrical double-trench MOSFETs for a wide range of temperatures in comparison with SiC planar MOSFETs. The magnitude of gate stress are within the recommended ranges by manufacturers with clear threshold voltage drift being observed. Also, the post-stress drift of on-state resistance at both high and low applied gate-source voltages is measured. The impact of temperature on these parameters are shown to vary for different structured MOSFETs.

Original language	English
Title of host publication	PCIM Europe 2022
Subtitle of host publication	International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	1067-1072
Number of pages	6
ISBN (Print)	9783800758227
DOIs	https://doi.org/10.30420/565822148
Publication status	Published - 19 Aug 2022
Event	International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2022 - Nuremberg, Germany Duration: 10 May 2022 → 12 May 2022

Publication series

Name	PCIM Europe Conference Proceedings
ISSN (Electronic)	2191-3358

Conference

Conference	International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2022
Country/Territory	Germany
City	Nuremberg
Period	10/05/22 → 12/05/22

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Publisher Copyright:
© VDE VERLAG GMBH, Berlin, Offenbach.

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Yang, J., Jahdi, S., Stark, B., Mellor, P., Wu, R., Ortiz-Gonzalez, J., & Alatise, O. (2022). Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress. In PCIM Europe 2022: International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (pp. 1067-1072). (PCIM Europe Conference Proceedings). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.30420/565822148

Yang, Juefei ; Jahdi, Saeed ; Stark, Bernard et al. / Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress. PCIM Europe 2022: International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management. Institute of Electrical and Electronics Engineers (IEEE), 2022. pp. 1067-1072 (PCIM Europe Conference Proceedings).

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abstract = "In this paper, long-period positive and negative DC gate bias stressing is applied on the SiC symmetrical and asymmetrical double-trench MOSFETs for a wide range of temperatures in comparison with SiC planar MOSFETs. The magnitude of gate stress are within the recommended ranges by manufacturers with clear threshold voltage drift being observed. Also, the post-stress drift of on-state resistance at both high and low applied gate-source voltages is measured. The impact of temperature on these parameters are shown to vary for different structured MOSFETs.",

author = "Juefei Yang and Saeed Jahdi and Bernard Stark and Phil Mellor and Ruizhu Wu and Jose Ortiz-Gonzalez and Olayiwola Alatise",

note = "Publisher Copyright: {\textcopyright} VDE VERLAG GMBH, Berlin, Offenbach.; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2022 ; Conference date: 10-05-2022 Through 12-05-2022",

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Yang, J, Jahdi, S , Stark, B , Mellor, P, Wu, R, Ortiz-Gonzalez, J & Alatise, O 2022, Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress. in PCIM Europe 2022: International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management. PCIM Europe Conference Proceedings, Institute of Electrical and Electronics Engineers (IEEE), pp. 1067-1072, International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, PCIM Europe 2022, Nuremberg, Germany, 10/05/22. https://doi.org/10.30420/565822148

Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress. / Yang, Juefei; Jahdi, Saeed ; Stark, Bernard et al.
PCIM Europe 2022: International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management. Institute of Electrical and Electronics Engineers (IEEE), 2022. p. 1067-1072 (PCIM Europe Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

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AU - Mellor, Phil

AU - Wu, Ruizhu

AU - Ortiz-Gonzalez, Jose

AU - Alatise, Olayiwola

PY - 2022/8/19

Y1 - 2022/8/19

N2 - In this paper, long-period positive and negative DC gate bias stressing is applied on the SiC symmetrical and asymmetrical double-trench MOSFETs for a wide range of temperatures in comparison with SiC planar MOSFETs. The magnitude of gate stress are within the recommended ranges by manufacturers with clear threshold voltage drift being observed. Also, the post-stress drift of on-state resistance at both high and low applied gate-source voltages is measured. The impact of temperature on these parameters are shown to vary for different structured MOSFETs.

AB - In this paper, long-period positive and negative DC gate bias stressing is applied on the SiC symmetrical and asymmetrical double-trench MOSFETs for a wide range of temperatures in comparison with SiC planar MOSFETs. The magnitude of gate stress are within the recommended ranges by manufacturers with clear threshold voltage drift being observed. Also, the post-stress drift of on-state resistance at both high and low applied gate-source voltages is measured. The impact of temperature on these parameters are shown to vary for different structured MOSFETs.

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Yang J, Jahdi S , Stark B , Mellor P, Wu R, Ortiz-Gonzalez J et al. Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress. In PCIM Europe 2022: International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management. Institute of Electrical and Electronics Engineers (IEEE). 2022. p. 1067-1072. (PCIM Europe Conference Proceedings). doi: 10.30420/565822148

Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress

Abstract

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Bibliographical note

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Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

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Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress

Abstract

Publication series

Conference

Bibliographical note

Access to Document

Handle.net

Other files and links

Fingerprint

Student theses

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Cite this