Towards Automating Simulation-Based Design Verification Using ILP

KI Eder; PA Flach; H-W Hsueh

doi:10.1007/978-3-540-73847-3_20

Towards Automating Simulation-Based Design Verification Using ILP

KI Eder, PA Flach, H-W Hsueh

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

14 Citations (Scopus)

Abstract

Increasing the productivity of simulation-based semiconductor design verification is one of the urgent challenges identified in the International Technology Roadmap for Semiconductors. The most difficult aspect is the generation of stimulus for functional coverage closure. This paper introduces a new Coverage-Directed test Generation (CDG) feedback loop which applies Inductive Logic Programming (ILP) to selected tests and coverage data to induce rules that can be used to automatically direct stimulus generation towards outstanding coverage. The case study documented in this paper shows a significant reduction of simulation time when ILP-based CDG is compared to random test generation. This is an exciting and promising new application area for ILP.

Translated title of the contribution	Towards Automating Simulation-Based Design Verification Using ILP
Original language	English
Title of host publication	Inductive Logic Programming, 16th International Conference, ILP 2006, Santiago de Compostela, Spain, August 24-27, 2006
Publisher	Springer
Pages	154 - 168
Number of pages	15
Volume	LNAI 4455
ISBN (Print)	9783540738466
DOIs	https://doi.org/10.1007/978-3-540-73847-3_20
Publication status	Published - Aug 2007

Bibliographical note

Other: Lecture Notes in Computer Science, vol 4455

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10.1007/978-3-540-73847-3_20

http://www.springerlink.com/content/c4042j772851ul49/

Cite this

@inproceedings{c2e1fc57fe2648c0914881f8ad7ed635,

title = "Towards Automating Simulation-Based Design Verification Using ILP",

abstract = "Increasing the productivity of simulation-based semiconductor design verification is one of the urgent challenges identified in the International Technology Roadmap for Semiconductors. The most difficult aspect is the generation of stimulus for functional coverage closure. This paper introduces a new Coverage-Directed test Generation (CDG) feedback loop which applies Inductive Logic Programming (ILP) to selected tests and coverage data to induce rules that can be used to automatically direct stimulus generation towards outstanding coverage. The case study documented in this paper shows a significant reduction of simulation time when ILP-based CDG is compared to random test generation. This is an exciting and promising new application area for ILP.",

author = "KI Eder and PA Flach and H-W Hsueh",

note = "Other: Lecture Notes in Computer Science, vol 4455",

year = "2007",

month = aug,

doi = "10.1007/978-3-540-73847-3_20",

language = "English",

isbn = "9783540738466",

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}

Towards Automating Simulation-Based Design Verification Using ILP. / Eder, KI ; Flach, PA; Hsueh, H-W.

Inductive Logic Programming, 16th International Conference, ILP 2006, Santiago de Compostela, Spain, August 24-27, 2006. Vol. LNAI 4455 Springer, 2007. p. 154 - 168.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - Towards Automating Simulation-Based Design Verification Using ILP

AU - Eder, KI

AU - Flach, PA

AU - Hsueh, H-W

N1 - Other: Lecture Notes in Computer Science, vol 4455

PY - 2007/8

Y1 - 2007/8

N2 - Increasing the productivity of simulation-based semiconductor design verification is one of the urgent challenges identified in the International Technology Roadmap for Semiconductors. The most difficult aspect is the generation of stimulus for functional coverage closure. This paper introduces a new Coverage-Directed test Generation (CDG) feedback loop which applies Inductive Logic Programming (ILP) to selected tests and coverage data to induce rules that can be used to automatically direct stimulus generation towards outstanding coverage. The case study documented in this paper shows a significant reduction of simulation time when ILP-based CDG is compared to random test generation. This is an exciting and promising new application area for ILP.

AB - Increasing the productivity of simulation-based semiconductor design verification is one of the urgent challenges identified in the International Technology Roadmap for Semiconductors. The most difficult aspect is the generation of stimulus for functional coverage closure. This paper introduces a new Coverage-Directed test Generation (CDG) feedback loop which applies Inductive Logic Programming (ILP) to selected tests and coverage data to induce rules that can be used to automatically direct stimulus generation towards outstanding coverage. The case study documented in this paper shows a significant reduction of simulation time when ILP-based CDG is compared to random test generation. This is an exciting and promising new application area for ILP.

U2 - 10.1007/978-3-540-73847-3_20

DO - 10.1007/978-3-540-73847-3_20

M3 - Conference Contribution (Conference Proceeding)

SN - 9783540738466

VL - LNAI 4455

SP - 154

EP - 168

BT - Inductive Logic Programming, 16th International Conference, ILP 2006, Santiago de Compostela, Spain, August 24-27, 2006

PB - Springer

ER -

Towards Automating Simulation-Based Design Verification Using ILP

Abstract

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