With Exascale machines on our immediate horizon, there is a pressing need for applications to be made ready to best exploit these systems. However, there will be multiple paths to Exascale, with each system relying on processor and accelerator technologies from different vendors. As such, applications will be required to be portable between these different architectures, but it is also critical that they are efficient too. These double requirements for portability and efficiency begets the need for performance portability. In this study we survey the performance portability of different programming models, including the open standards OpenMP and SYCL, across the diverse landscape of Exascale and pre-Exascale processors from Intel, AMD, NVIDIA, Fujitsu, Marvell, and Amazon, together encompassing GPUs and CPUs based on both x86 and Arm architectures. We also take a historical view and analyse how performance portability has changed over the last year.
|Title of host publication||Proceedings of the Performance Portability and Productivity Workshop P3HPC|
|Subtitle of host publication||Supercomputing 2020|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication status||Accepted/In press - 22 Sep 2020|
Deakin, T. J., Poenaru, A., Lin, T., & Mcintosh-Smith, S. N. (Accepted/In press). Tracking Performance Portability on the Yellow Brick Road to Exascale. In Proceedings of the Performance Portability and Productivity Workshop P3HPC: Supercomputing 2020 Institute of Electrical and Electronics Engineers (IEEE).