Abstract
We describe our high-speed hardware modules for the 14 candidates of the second evaluation round of the SHA-3 hash function competition. Emphasis has been put on bringing as many aspects of design and implementation as possible into agreement in order to receive consistent and comparable evaluation results. For most candidates we have tested a range of different design and implementation options. The evaluation involved a large number of synthesis runs in a uniform setup and under the use of a simple optimization heuristic. In addition to identifying good hardware-design options, this approach has yielded data on numerous possible area-performance tradeoffs for the different hardware modules. The best configurations then underwent place & route in order to reach the highest degree of accuracy of performance metrics short of actual implementation in silicon.
| Translated title of the contribution | Uniform Evaluation of Hardware Implementations of the Round-Two SHA-3 Candidates |
|---|---|
| Original language | English |
| Title of host publication | The Second SHA-3 Candidate Conference |
| Publisher | NIST |
| Pages | - |
| Volume | - |
| Publication status | Published - 2010 |
Bibliographical note
Other page information: -Conference Proceedings/Title of Journal: The Second SHA-3 Candidate Conference
Other identifier: 2001240