Abstract
The paper presents a hands-on method that demonstrates how to use a formal
property checker to analyse code coverage holes left by module-level simulation
in order to achieve early code coverage closure. The core principle of the
method is based on temporal induction. The method is fully automatic and
generic in that it can be implemented with any state-of-the-art formal property
checker.
Translated title of the contribution | Using a Formal Property Checker for Simulation Coverage Closure |
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Original language | English |
Title of host publication | Design Automation Conference |
Publication status | Published - 2010 |
Bibliographical note
Other page information: -Conference Proceedings/Title of Journal: Design Automation Conference
Other identifier: 2001219