Using a Formal Property Checker for Simulation Coverage Closure

Tim Blackmore; David Halliwell; Phil Barker; Kerstin Eder; Naresh Ramaram

Using a Formal Property Checker for Simulation Coverage Closure

Tim Blackmore
, David Halliwell
, Phil Barker
, Kerstin Eder
, Naresh Ramaram

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

Abstract

The paper presents a hands-on method that demonstrates how to use a formal property checker to analyse code coverage holes left by module-level simulation in order to achieve early code coverage closure. The core principle of the method is based on temporal induction. The method is fully automatic and generic in that it can be implemented with any state-of-the-art formal property checker.

Translated title of the contribution	Using a Formal Property Checker for Simulation Coverage Closure
Original language	English
Title of host publication	Design Automation Conference
Publication status	Published - 2010

Bibliographical note

Other page information: -
Conference Proceedings/Title of Journal: Design Automation Conference
Other identifier: 2001219

Access to Document

http://www.cs.bris.ac.uk/Publications/pub_master.jsp?id=2001219

Handle.net

Persistent link

Cite this

@inproceedings{56ffe67b796942b993751de4bace12b7,

title = "Using a Formal Property Checker for Simulation Coverage Closure",

abstract = "The paper presents a hands-on method that demonstrates how to use a formal property checker to analyse code coverage holes left by module-level simulation in order to achieve early code coverage closure. The core principle of the method is based on temporal induction. The method is fully automatic and generic in that it can be implemented with any state-of-the-art formal property checker. ",

author = "Tim Blackmore and David Halliwell and Phil Barker and Kerstin Eder and Naresh Ramaram",

note = "Other page information: - Conference Proceedings/Title of Journal: Design Automation Conference Other identifier: 2001219",

year = "2010",

language = "English",

booktitle = "Design Automation Conference",

}

TY - GEN

T1 - Using a Formal Property Checker for Simulation Coverage Closure

AU - Blackmore, Tim

AU - Halliwell, David

AU - Barker, Phil

AU - Eder, Kerstin

AU - Ramaram, Naresh

N1 - Other page information: - Conference Proceedings/Title of Journal: Design Automation Conference Other identifier: 2001219

PY - 2010

Y1 - 2010

N2 - The paper presents a hands-on method that demonstrates how to use a formal property checker to analyse code coverage holes left by module-level simulation in order to achieve early code coverage closure. The core principle of the method is based on temporal induction. The method is fully automatic and generic in that it can be implemented with any state-of-the-art formal property checker.

AB - The paper presents a hands-on method that demonstrates how to use a formal property checker to analyse code coverage holes left by module-level simulation in order to achieve early code coverage closure. The core principle of the method is based on temporal induction. The method is fully automatic and generic in that it can be implemented with any state-of-the-art formal property checker.

M3 - Conference Contribution (Conference Proceeding)

BT - Design Automation Conference

ER -

Using a Formal Property Checker for Simulation Coverage Closure

Abstract

Bibliographical note

Access to Document

Handle.net

Fingerprint

Cite this