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Memristor is an emerging non-volatile memory device that features smaller size and hybrid memristor/CMOS integration, which maximizes the advantages of high density and versatility. In this paper we utilize the memristor as weights and its state change behavior to capture some of the potential faults in a system. Photovoltaic arrays are taken as an example for the study. We will demonstrate that the state variations can be mapped into a timing which can be used as useful information for behavior of the system under measurement. Empirical studies are carried out using Spice based simulations to investigate into the impact of biasing and threshold voltages on timing behavior. Underpinning these studies, a relationship between input voltage and memristor state transition is proposed and extensively validated through further simulations to identify specific faulty behavior.
|Title of host publication||Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||6|
|Publication status||Published - 18 Nov 2014|
|Event||27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014 - Amsterdam, United Kingdom|
Duration: 1 Oct 2014 → 3 Oct 2014
|Conference||27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014|
|Period||1/10/14 → 3/10/14|
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- 1 Finished
Yield and reliability enhancement techniques for novel memory devices
Pradhan, D. K.
24/08/12 → 24/12/15