As technology scales down to nanometer regime the process variations have profound effect on circuit characteristics. Meeting timing and power constraints under such process variations in nano-CMOS circuit design is increasingly difficult. This causes a shifting from worst-case based analysis and optimization to statistical or probability based analysis and optimization at every level of circuit abstraction. This paper presents a TED (Taylor Expansion Diagram) based -multi-Tox techniques during high-level synthesis (HLS). A variation-aware simultaneous scheduling and resource binding algorithm is proposed which maximizes the power yield under timing yield and performance constraint. For this purpose, a-multi-Tox library is characterized under process variation. The delay and power distribution of different functional units are exhaustively studied. The proposed variation-aware algorithm uses those components for generating low power RTL under a given timing yield and performance constraint. The experimental results show significant improvement as high as 95% on leakage power yield under given constraints.
|Translated title of the contribution||Variation-Aware TED- Based Approach for Nano-CMOS RTL Leakage Optimization|
|Title of host publication||2011 24th International Conference on VLSI Design (VLSI Design)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication status||E-pub ahead of print - 22 Feb 2011|
Bibliographical noteISBN: 10638210
Name and Venue of Conference: IEEE 24th International Conference on VLSI Design
Other identifier: 2001383