WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors

Theoni Alexoudi, Dimitrios Fitsios, Pavlos Maniotis, Chris Vagionas, Sotirios Papaioannou, Amalia Miliou, George T. Kanellos, Nikos Pleros

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

2 Citations (Scopus)

Abstract

The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known 'Memory Wall' problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.

Original languageEnglish
Title of host publicationICTON 2015 - 17th International Conference on Transparent Optical Networks
PublisherIEEE Computer Society
Volume2015-August
ISBN (Electronic)9781467378802
DOIs
Publication statusPublished - 1 Jan 2015
Event17th International Conference on Transparent Optical Networks, ICTON 2015 - Budapest, Hungary
Duration: 5 Jul 20159 Jul 2015

Conference

Conference17th International Conference on Transparent Optical Networks, ICTON 2015
CountryHungary
CityBudapest
Period5/07/159/07/15

Keywords

  • Access gate (AG)
  • Column decoder (CD)
  • Optical memory
  • RAM
  • Row decoder (RD)
  • Semiconductor optical amplifier (SOA)
  • Silicon technology

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