WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors

Theoni Alexoudi; Dimitrios Fitsios; Pavlos Maniotis; Chris Vagionas; Sotirios Papaioannou; Amalia Miliou; George T. Kanellos; Nikos Pleros

doi:10.1109/ICTON.2015.7193417

WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors

Theoni Alexoudi, Dimitrios Fitsios, Pavlos Maniotis, Chris Vagionas, Sotirios Papaioannou, Amalia Miliou, George T. Kanellos, Nikos Pleros

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

3 Citations (Scopus)

Abstract

The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known 'Memory Wall' problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.

Original language	English
Title of host publication	ICTON 2015 - 17th International Conference on Transparent Optical Networks
Publisher	IEEE Computer Society
Volume	2015-August
ISBN (Electronic)	9781467378802
DOIs	https://doi.org/10.1109/ICTON.2015.7193417
Publication status	Published - 1 Jan 2015
Event	17th International Conference on Transparent Optical Networks, ICTON 2015 - Budapest, Hungary Duration: 5 Jul 2015 → 9 Jul 2015

Conference

Conference	17th International Conference on Transparent Optical Networks, ICTON 2015
Country/Territory	Hungary
City	Budapest
Period	5/07/15 → 9/07/15

Keywords

Access gate (AG)
Column decoder (CD)
Optical memory
RAM
Row decoder (RD)
Semiconductor optical amplifier (SOA)
Silicon technology

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Alexoudi, T., Fitsios, D., Maniotis, P., Vagionas, C., Papaioannou, S., Miliou, A., Kanellos, G. T., & Pleros, N. (2015). WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors. In ICTON 2015 - 17th International Conference on Transparent Optical Networks (Vol. 2015-August). Article 7193417 IEEE Computer Society. https://doi.org/10.1109/ICTON.2015.7193417

@inproceedings{3b822d0d1f2d4cb282c4cb5e9c590192,

title = "WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors",

abstract = "The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known 'Memory Wall' problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.",

keywords = "Access gate (AG), Column decoder (CD), Optical memory, RAM, Row decoder (RD), Semiconductor optical amplifier (SOA), Silicon technology",

author = "Theoni Alexoudi and Dimitrios Fitsios and Pavlos Maniotis and Chris Vagionas and Sotirios Papaioannou and Amalia Miliou and Kanellos, {George T.} and Nikos Pleros",

year = "2015",

month = jan,

day = "1",

doi = "10.1109/ICTON.2015.7193417",

language = "English",

volume = "2015-August",

booktitle = "ICTON 2015 - 17th International Conference on Transparent Optical Networks",

publisher = "IEEE Computer Society",

address = "United States",

note = "17th International Conference on Transparent Optical Networks, ICTON 2015 ; Conference date: 05-07-2015 Through 09-07-2015",

}

Alexoudi, T, Fitsios, D, Maniotis, P, Vagionas, C, Papaioannou, S, Miliou, A, Kanellos, GT & Pleros, N 2015, WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors. in ICTON 2015 - 17th International Conference on Transparent Optical Networks. vol. 2015-August, 7193417, IEEE Computer Society, 17th International Conference on Transparent Optical Networks, ICTON 2015, Budapest, Hungary, 5/07/15. https://doi.org/10.1109/ICTON.2015.7193417

WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors. / Alexoudi, Theoni; Fitsios, Dimitrios; Maniotis, Pavlos et al.
ICTON 2015 - 17th International Conference on Transparent Optical Networks. Vol. 2015-August IEEE Computer Society, 2015. 7193417.

Research output: Chapter in Book/Report/Conference proceeding › Conference Contribution (Conference Proceeding)

TY - GEN

T1 - WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors

AU - Alexoudi, Theoni

AU - Fitsios, Dimitrios

AU - Maniotis, Pavlos

AU - Vagionas, Chris

AU - Papaioannou, Sotirios

AU - Miliou, Amalia

AU - Kanellos, George T.

AU - Pleros, Nikos

PY - 2015/1/1

Y1 - 2015/1/1

N2 - The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known 'Memory Wall' problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.

AB - The rapid increase in processor throughput is currently exceeding the electronic memory speed progress, forming the well-known 'Memory Wall' problem, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work spanning from WDM-enabled optical RAM bank architectures with optical all-passive row/column decoder modules to a complete 16GHz optical cache memory physical layer design for Chip Multiprocessor configurations and up to the Si-based integrated optical RAM cell architectures currently pursued within the FP7 RAMPLAS project.

KW - Access gate (AG)

KW - Column decoder (CD)

KW - Optical memory

KW - RAM

KW - Row decoder (RD)

KW - Semiconductor optical amplifier (SOA)

KW - Silicon technology

UR - http://www.scopus.com/inward/record.url?scp=84940909940&partnerID=8YFLogxK

U2 - 10.1109/ICTON.2015.7193417

DO - 10.1109/ICTON.2015.7193417

M3 - Conference Contribution (Conference Proceeding)

AN - SCOPUS:84940909940

VL - 2015-August

BT - ICTON 2015 - 17th International Conference on Transparent Optical Networks

PB - IEEE Computer Society

T2 - 17th International Conference on Transparent Optical Networks, ICTON 2015

Y2 - 5 July 2015 through 9 July 2015

ER -

WDM-enabled optical RAM and optical cache memory architectures for Chip Multiprocessors

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Keywords

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