Abstract
The processor-memory performance gap, commonly referred to as 'Memory Wall' problem, owes to the speed mismatch between processor and electronic RAM clock frequencies. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work on optical RAM cell configurations exploiting silicon-based integrated switching and latching elements with SOAs serving as the active devices. We review both their experimental and underlying theoretical framework and proceed with the demonstration of new optical cache architectural paradigms enabled by the introduction of WDM principles in the storage area. The higher than 40GHz optical RAM cell operational speeds and the WDM-enabled cache architectures comprise two major factors towards realizing ultra-fast and low-power CPU-memory communication.
Original language | English |
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Title of host publication | 2013 15th International Conference on Transparent Optical Networks, ICTON 2013 |
DOIs | |
Publication status | Published - 15 Oct 2013 |
Event | 2013 15th International Conference on Transparent Optical Networks, ICTON 2013 - Cartagena, Spain Duration: 23 Jun 2013 → 27 Jun 2013 |
Conference
Conference | 2013 15th International Conference on Transparent Optical Networks, ICTON 2013 |
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Country/Territory | Spain |
City | Cartagena |
Period | 23/06/13 → 27/06/13 |
Keywords
- access gate (AG)
- column decoder (CD)
- optical memory
- optical RAM
- row decoder
- semiconductor optical amplifier (SOA)
- silicon technology