Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB

Rafael Asenjo, Angeles Navarro, Andres Rodriguez, Jose Nunez-Yanez

Research output: Chapter in Book/Report/Conference proceedingConference Contribution (Conference Proceeding)

1 Citation (Scopus)
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In this paper we evaluate the performance and energy effectiveness of FPGA and CPU devices for parallel computing problems in which the workload can be distributed in a novel way to enable simultaneous computing in addition to simple off loading.  The FPGA device is programmed via OpenCL using the recent availability of commercial tools and hardware while Threading Building Blocks (TBB) is used to orchestrate the load distribution and balancing between FPGA and the multicore CPU. We present an approach that allows the user to specify the type of parallelism exploited by each pipeline stage running in the CPU, the mapping of the pipeline stages to the devices (FPGA or CPU) and the number of active threads. Using as case of study a real streaming application, we evaluate how these parameters affect the performance and energy efficiency using as reference a heterogeneous system that includes four different types of computational resources: a quad-core Intel Haswell CPU, an embedded Intel HD6000 GPU, a discrete NVIDIA GPU and an Altera FPGA.
Original languageEnglish
Title of host publicationParallel Computing
Subtitle of host publicationOn the Road to Exascale
EditorsGerhard R Joubert, Hugh Leather, Mark Parsons, Frans Peters, Mark Sawyer
PublisherIOS Press
Number of pages9
ISBN (Electronic)9781614996217
ISBN (Print)9781614996200
Publication statusPublished - 1 Sept 2015
EventInternational Conference on Parallel Computing (ParCo) 2015 - Edinburgh, United Kingdom
Duration: 1 Sept 20154 Sept 2015

Publication series

NameAdvances in Parallel Computing
PublisherIOS Press
ISSN (Print)0927-5452
ISSN (Electronic)1879-808X


ConferenceInternational Conference on Parallel Computing (ParCo) 2015
Country/TerritoryUnited Kingdom


  • FPGA
  • Heterogeneous scheduling
  • OpenCL
  • Streaming application


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  • OpenCL-FPGA study for ASEArch

    Nunez-Yanez, J. L.


    Project: Research

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