Workload distribution and balancing in FPGAs and CPUs with OpenCL and TBB

In this paper we evaluate the performance and energy effectiveness of FPGA and CPU devices for parallel computing problems in which the workload can be distributed in a novel way to enable simultaneous computing in addition to simple off loading.  The FPGA device is programmed via OpenCL using the recent availability of commercial tools and hardware while Threading Building Blocks (TBB) is used to orchestrate the load distribution and balancing between FPGA and the multicore CPU. We present an approach that allows the user to specify the type of parallelism exploited by each pipeline stage running in the CPU, the mapping of the pipeline stages to the devices (FPGA or CPU) and the number of active threads. Using as case of study a real streaming application, we evaluate how these parameters affect the performance and energy efficiency using as reference a heterogeneous system that includes four different types of computational resources: a quad-core Intel Haswell CPU, an embedded Intel HD6000 GPU, a discrete NVIDIA GPU and an Altera FPGA.