Algorithm Development for the CMS Level-1 Trigger at the High-Luminosity LHC

Abstract

The upgrade of the Large Hadron Collider (LHC) at the European Organisation for Nuclear
Research (CERN) to the High-Luminosity LHC, will provide a larger number of simultaneous
proton-proton collisions, and will provide more data for physics analysis. However, this will
challenge the level-1 (L1) trigger selections. Tracking information will be provided to the
L1 hardware trigger to mitigate these challenges. The CMS L1 track-finding chain aims to
reconstruct the tracks of charged particles with pT > 2 GeV, within 4 µs. Due to parallel ϕ
sector processing in the detector, where there is the seeding of tracks in multiple outer tracker
layers simultaneously, duplicate tracks may arise in the track-finding chain. A Track Merger
firmware algorithm will be presented in this thesis, which is designed to remove duplicate tracks
before the re-fit of track parameters in the Kalman Filter. The design was tested targeting a
Xilinx VU13P Field Programmable Gate Array (FPGA) and met the timing requirements of
the L1 track reconstruction latency budget.
In addition, a L1 trigger firmware algorithm designed to compute missing hadronic energy
(Hmiss
T
) will be presented in this thesis. This firmware algorithm uses the outputs of the Phase-2
Jets and Sums algorithm that is designed to reconstruct jets in the L1 Correlator Layer-2
trigger. The Hmiss
T
algorithm was demonstrated on a Xilinx KU15P FPGA and the design met
the timing requirements of the L1 trigger, obtaining a 100% FPGA output - software emulation
agreement over 50,000 events. The physics performance of the Hmiss
T
algorithm was studied, and
similar performance was found for different jet finder implementations for the rate, resolution,
and efficiency of the algorithm.

Date of Award	3 Oct 2023
Original language	English
Awarding Institution	University of Bristol
Supervisor	Joel Goldstein (Supervisor) & Sudarshan Paramesvaran (Supervisor)