Design, Fabrication and Characterisation of Micro and Nano-electromechanical(MEM/NEM) Relays for Circuit Applications

Abstract

Complementary Metal-Oxide-Semiconductor (CMOS) technology remains foundational to
advancements in computing; however, as device scaling reaches physical limits, CMOS
technology faces increasing challenges, especially concerning power dissipation and leakage
currents. These limitations are particularly problematic under high-temperature or radiationintensive
conditions, which are critical for emerging applications such as the Internet of Things
(IoT), and edge computing. Given the pressing need for more efficient computing architectures,
significant research efforts have been directed toward beyond-CMOS technologies.
Several beyond-CMOS technologies are being explored to address the limitations of CMOS.
Among candidates, micro- and nano-electromechanical (MEM/NEM) relays are particularly
promising due to their zero standby leakage, dual functionality in logic and memory, and compatibility
with current semiconductor manufacturing, making them viable candidates for ultra-lowpower
applications and a strong alternative in scenarios where CMOS faces scaling and power
constraints. However, existing research efforts have not sufficiently advanced the investigation of
large-scale MEM/NEM computing circuits or their fundamental understanding.
To address this, this research makes several key advancements toward establishing MEM/NEM
relays as stable, reliable devices for ultra-low-power computing. The first major contribution is
the development of a robust fabrication process for three critical MEM relay devices, addressing
challenges such as vertical sidewall formation, suspension mechanics, and material compatibility.
The second contribution focuses on a detailed architectural exploration to improve in-plane relay
stability and reliability. This includes optimizing structural rigidity, defining safe operational
thresholds to prevent overdrive, resolving snap-in instability to minimize wear, and reducing
pull-in voltage to lower power consumption. Another significant contribution is a detailed mechanical
analysis that supports the functionality of the ambipolar relay, successfully addressing
the pull-down failure mechanism. Building on these advancements, this research implements
essential circuit components, such as Look-Up Table (LUT) memory cells and inverters, using
entirely relay-based designs. Furthermore, it demonstrates the scalability of MEM relays to
NEM relays, paving the way for the development of next-generation, ultra-low-power relay-based
computing systems.
Another major contribution of this Ph.D. research to MEM/NEM relay-based computing is a
comprehensive analysis of energy consumption, beginning from first principles and validated
through measurements on silicon MEM relay prototypes. This work thoroughly investigates the
different components contributing to energy consumption in MEM/NEM relays, including the
dynamic energy required for charging the gate capacitance and the static energy lost through
substrate leakage. The models, analyses, and measurement methodologies developed here form a
foundational set of tools for accurately estimating the energy consumption of MEM/NEM relays
in ultra-low-power circuit applications.

Date of Award	4 Feb 2025
Original language	English
Awarding Institution	University of Bristol
Supervisor	I D B Pamunuwa (Supervisor)