Abstract
The rapid rise in global energy demand, coupled with mounting environmental concerns,necessitates exploring alternatives to traditional silicon-based electronics. (Ultra)wide
bandgap semiconductors, particularly AlGaN/GaN-based heterostructures and β type
Ga2O3 devices present compelling solutions. The devices based on these materials enable higher
breakdown voltages and greater power densities, positioning them as a promising alternative
to conventional silicon technologies. For now, commercial GaN-based devices are competitive
with the silicon carbide (SiC)-based devices in high-voltage applications especially within voltage
ranges between 650V and 1200 V. State-of-the-art material solutions such as GaN-on-QST are
proposed for enabling mass production and further increasing the blocking voltage of GaN device
technology. Recently β type Ga2O3 devices, such as lateral β type Ga2O3 MOSFET, have gained
significant attention due to the extremely high theoretical Baliga’s Figure of merit (BFOM) large
and the cost advantages. However, challenges related to their electrical and thermal reliability
need to be addressed for the devices based on both the materials, which is significant as a basis
to be able to occupy a large market share of consumer and industrial applications.
In this thesis, the electrical reliability of the AlGaN/GaN-based E-mode high-electron-mobility
transistor (HEMTs) on the 200 mm QST⃝R
substrate is investigated. By conducting electrical
characterization of GaN-on-QST power HEMTs (target 650 to 1200 V), a ’kink’ effect in the output
characteristics was observed, this was attributed to the heavily doped carbon density of the GaN:
C buffer layer. By using back biasing measurements on the transfer length method (TLM)
structures, a time-dependent conduction mechanism was identified from an undulation in the
reversed stepped superlattice (RSSL) layer. It is attributed to a localized trap-assisted vertically
conduction process and then spread out laterally in the RSSL layer when the devices were
operated with substrate bias of ∼-300 V for 101
to 103
s. The formation of the conduction path is
related to trap-assisted leakage through the superlattice (SL) layers on the engineered substrates;
de-trapped carriers spread out vertically and laterally within a portion of the SLs, leading to a
higher electrical field across the rest of the layers. In addition, the thermal performance of the
GaN-on-QST power HEMTs on the 200 mm QST⃝R
substrate was measured and compared with
the same type devices on the Si substrates. The thermal conductivity of the SL and the buried
oxide layer (BOX) on the QST⃝R
substrate are extracted through Raman thermography and 3-D
finite element method (FEM) thermal simulations. The steady-state channel temperatures of
the devices were measured and simulated, which shows the thermal resistance of large area
transistors on QST⃝R
is up ∼1/3 lower than equivalent transistors on GaN-on-Si substrates.
The transient thermal simulation indicates that the QST⃝R
substrates have a higher thermal
impedance than Si substrates between 10 µs and 1 ms, considering that QST⃝R
substrates
contain a thick buried oxide layer. Device thermal simulation shows that no significant heat will
accumulate for the devices on both Si and QST⃝R
substrates between 100k and 1MHz switching
frequency.
Si contaminants at the epitaxial/substrate interface of a lateral β-Ga2O3 MOSFET significantly affect the device electrical performance, e.g., the breakdown voltages and the off-state
leakage current. In this thesis, we investigated a lateral β-Ga2O3 MOSFET with a parallel
leakage path at the epilayer/substrate interface due to the unintentional Si impurities. Fe ions
are implanted to compensate for those Si-impurities before the epilayer growth and the wafer
is annealed together after the epilayer growth. A frequency dispersion of impedance of this
lateral β-Ga2O3 MOSFET is observed and characterized, which could be explained by resistive
and capacitive (RC) coupling between terminal contact pads and the buried conducting layer
associated with Si contaminant at the epitaxy/substrate interface. By building an equivalent
RC network, the mobility of the buried channel of the devices could be estimated when fitting
with the experimental data. In addition, a significant instability in threshold voltage (hysteresis)
during on/off switching of this lateral β-Ga2O3 MOSFET was observed, which could be attributed
to traps inside the unintentionally doped (UID) buffer layer with an activation energy of 0.25 ±
0.04 eV, extracted using temperature-dependent current-voltage measurements complemented
by with technology computer-aided design (TCAD) simulations. These trap states enhance the
vertical conductivity of the UID buffer layer under high gate electrical fields, enabling charge flow
through the buried channel at the epilayer/substrate interface when the Si impurities are not
perfectly compensated by the implanted Fe. The origin of the traps inside the UID seems highly
related to the Fe ions implanted before epilayer growth. This vertical part of the leakage path
dominates the leakage behavior of the device in the off-state, giving rise to an elevated off-state
leakage current. Our findings highlight the importance of considering not only the compensation
of the Si impurities at the epilayer/substrate interfaces but also the role of traps inside the UID
β-Ga2O3 epilayer, after compensating the Si impurities by Fe implantation.
| Date of Award | 13 May 2025 |
|---|---|
| Original language | English |
| Awarding Institution |
|
| Supervisor | Matthew D Smith (Supervisor) & Martin H H Kuball (Supervisor) |