Failure and Degradation Analysis of Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Stress

Abstract

The superior material properties of SiC enable SiC MOSFETs to enhance power density and system efficiency. However, the reliability of SiC MOSFETs under extreme conditions, such as short circuit events, remains a concern. To improve the understanding
of short circuit reliability, this thesis conducts short circuit tests on planar, symmetrical double-trench, and asymmetrical trench SiC MOSFETs, investigates the parameter
degradation of three types of devices under different temperatures, studies the reliability differences in parallel SiC MOSFETs with intrinsic and layout parameter mismatches
under various voltages, and characterizes the short circuit safe operating area (SCSOA).
Firstly, the short circuit reliability of devices with different structures is compared. The
degradation patterns of static and dynamic parameters and the underlying mechanisms
are studied. The planar SiC MOSFET tested at 300 K showed no degradation after
5000 cycles, while the device tested at 450 K had an increase in on-state resistance (Ron).
Symmetrical double-trench and asymmetrical trench SiC MOSFETs degraded after tens
and hundreds of impulses, respectively. The degradation of threshold voltage (V th) and
gate-source leakage current (I gss) contributed to the degradation of dynamic parameters.
The failure of trench SiC MOSFETs was attributed to the high electro-thermal stress in
the gate oxide, with elevated test temperatures accelerating the degradation.
Then, the influence of intrinsic parameter mismatches (V th and Ron) on the reliability
of parallel SiC MOSFETs is studied under various drain-source voltages (V ds) and short
circuit durations (t sc). Although the current imbalance was significant in parallel planar
SiC MOSFETs, the devices demonstrated high reliability without failure under all test
conditions. The instability of symmetrical double-trench SiC MOSFETs led to varying
degradation relationships. For parallel asymmetrical trench SiC MOSFETs, differences
in current and short circuit energy (Esc) caused distinct degradation rates.
Next, the impact of layout parameter mismatches on the short circuit reliability of
parallel devices is discussed, including gate resistance (Rg) and case temperature (Tcase).
Both planar SiC MOSFETs exhibited high reliability, while parallel symmetrical doubletrench SiC MOSFETs showed similar reliability under Rg mismatch condition. The difference in Rg led to asynchronous degradation in asymmetrical trench SiC MOSFETs.
Under different Tcase conditions, all devices tested at a higher temperature showed reduced reliability. The initial temperature had a more direct impact on the reliability.
Finally, the SCSOA of trench SiC MOSFETs is characterized across a range of t sc
and V ds. The number of cycles to failure correlated with Esc. Numerical models were
fitted to describe the relationship between failure cycles and test conditions for single
devices. When Esc remained low, trench devices demonstrated high reliability without
failure. However, when devices operated beyond the SCSOA, even slight variations in Esc
caused reliability disparities, which explained the differences in parallel configurations.
The research enhances the understanding of the short circuit reliability in SiC MOSFETs with different structures and provides insights for reliability assessmen

Date of Award	17 Jun 2025
Original language	English
Awarding Institution	University of Bristol
Supervisor	Saeed Jahdi (Supervisor) & Phil H Mellor (Supervisor)