Investigation into Accelerated Power Cycling of GaN HEMTs

Abstract

Power cycling is an accelerated thermal reliability test that is used to evaluate the longevity of power semiconductor devices. Repeated heating and cooling stress material interfaces, leading to device failure. Cycle durations take the order of tens of seconds, and failure results typically occur after several months of testing. The question arises of how much this artificial ageing process could be accelerated, whether real-time degradation could be observed, and whether this data could be used to predict the state of health in working power converters.
This thesis explores how to shorten cycle durations through closed-loop regulation of junction temperature, to provide a desired temperature swing at the substrate to lead frame interface in a GaN device. It explores the upper limit of heating power, where the temperature cycling loses effectiveness, and investigates the real-time observation of device degradation. An experimental facility is developed that cycles a commercial, 190 mΩ, 600 V GaN HEMT inside a half-bridge, which allows the heating power to be augmented by switching frequency. The resulting sub-second heating durations are terminated using turn-on di/dt as the temperature indicator. The accuracy of the indicator is investigated using continuous and double pulse tests to an error margin of 4°C. The interdependencies of heating power, cooling design, cycle durations, and junction temperature swing are derived, and illustrated with results from two cooling systems that both produce a 100°C junction temperature swing, but with different temperature swings at the Silicon substrate to lead frame interface (56°C and 89°C).
To validate the junction temperature measurement via peak di/dt, and to determine the temperature ranges over which specific locations inside a package are being subjected to, a 3D finite element model of a GaN HEMT is developed. This allows the exploration of the propagation of heat through the structure under power cycling conditions. The model is validated experimentally using thermal camera and thermocouple measurements. The model allows the determination of temperature distributions and cycle durations, showing that the cycle duration can be squeezed to 0.3 s in simulation. Experimentally, 1.8 s is achievable due to the minimum feedback time imposed by the control hardware.
A total of 8 GaN devices are characterised throughout the cycling, using a variety of methods, whilst ensuring that these are minimally invasive. IV characterisations, thermal resistance evaluations and isolated power cycles are performed between cycling. Most characterisations show single-digit percentage changes except for one device with up to 2 times increase in its thermal resistance. However, for 5 devices tested at a lead frame temperature swing of 89°C, the closed-loop controlled heating and cooling durations show an unstable phase, at least 5000 cycles prior to device failure, hinting at degradation at the gate network. These may provide the basis for future early warning systems or even health prediction methods. Devices are cycled between 15,000 to 120,000 cycles before failure, with test times taking less than a week. For 3 devices tested at a lead frame temperature swing of 56°C, no degradation is observed for more than 400,000 cycles. The accelerated AC power cycling results show that a lower lead frame swing leads to long device lifetime, while a high lead frame swing could cause new device failure mechanisms with test times of less than a week.

Date of Award	30 Sept 2025
Original language	English
Awarding Institution	University of Bristol
Sponsors	Toshiba Research Europe Ltd
Supervisor	Bernard H Stark (Supervisor) & Saeed Jahdi (Supervisor)