Investigation into Gate Current Profiles for Active Gate Driving of a SiC MOSFET Bridge-leg

Abstract

Active gate driving provides an effective means to control the switching transients of wide bandgap power devices, thereby mitigating issues such as voltage and current overshoot as well as ringing. With the emergence of smart, programmable gate drivers, the challenge remains of how to determine driver control parameters to effectively address specific switching issues. This thesis presents a windowed gate current profile optimisation method that is suitable for a range of driver concepts without requiring complex algorithms.
The method begins by measuring gate current profiles from a commercial non-active gate driver and varying the gate current profile within a defined time window. The window is divided into smaller segments in which the gate current amplitude is adjusted within the hardware limits of the active driver. The optimisation is carried out in simulation, where resulting switching waveforms are evaluated based on overshoot, ringing and switching losses. To ensure accurate predictions, the commercial SiC MOSFET device model is modified—specifically its nonlinear capacitances, reverse recovery behaviour, and high-power output characteristics. These modifications significantly improve the agreement between simulated and measured power loop and gate switching waveforms and energy losses, with errors in loss predictions being below 10 % for turn-on and 15 % for turn-off across a range of gate resistances.
Experimental validation is conducted using a new single-chip digital driver capable of synthesising arbitrary current waveforms. This application-specific integrated circuit (ASIC) features internal memory for two programmable gate sequences, supports 255 discrete current levels in both polarities, offers a waveform update resolution of up to 1.2 ns, and delivers gate voltage swings exceeding 36 V—suitable for driving SiC devices. A dedicated high-bandwidth testbed, including peripheral circuits and a programming system, is developed to enable robust waveform shaping under ultra-fast switching conditions while ensuring immunity to generated transients. High-bandwidth current sensing confirms the driver’s ability to accurately emulate and synthesize gate profiles.
The optimised gate profiles are implemented and experimentally validated on a 1200 V, 17 A SiC MOSFET in an 800 V, 10 A bridge-leg configuration. To further assess robustness, power loop inductance is varied. The modified model shows good agreement with measurements, and the optimised gate profiles supress 180 MHz turn-on current ringing by 7 dB and reduce turn-off voltage overshoot by 20 %, without increasing switching losses. The experimentally identified optimal profiles align closely with simulation predictions.
This work demonstrates computationally efficient gate profile optimisation, with strong potential for application in smart gate drivers.

Date of Award	9 Dec 2025
Original language	English
Awarding Institution	University of Bristol
Supervisor	Bernard H Stark (Supervisor) & Saeed Jahdi (Supervisor)