Abstract
Modern computing has come across a series of limitations that have indicated the end of Moore’s Law. In the past, advances in hardware design and fabrication processes provided a seemingly free lunch doubling performance every two years from continual miniaturisation at the device level without any major tradeoffs. However, this is no longer true and any further advancements need to face a compromise between power, performance, price, and area. Computation has split into two distinct fields: specialist high performance systems, and low power edge systems. The first prioritises performance over everything else, while the latter strives for low power and low cost embedded systems for use in less controlled environments. Both approaches are limited by of power consumption in their own context, but the focus of this work is on the development of low power edge computing systems.While other technologies have been proposed for low power systems, such as memristors and photonics, they have their own challenges. Functionally equivalent to transistors and compatible with standard manufacturing processes, electromechanical relays have the potential to solve some of the issues faced in systems at the edge. Their low leakage is able to dramatically increase the power efficiency of any system, and the lack of a channel as in solid-state devices, replaced by a physical air-gap, offers resistance to harsh environments where extreme temperatures and elevated radiation levels are prevalent. This makes relay based systems suitable for deployment in demanding applications beyond the capabilities of CMOS, such as in space exploration, nuclear decommissioning, and even in factory machinery.
This work brings mechanical relay technology to the forefront of integrated circuit design. A complete electronic design automation toolkit has been developed covering the full stack from abstract hardware descriptions of circuits and systems down to individual relay geometry design and physical simulation. This includes a top-down, hierarchical, system design methodology built upon a series of standard cells, allowing for both manual and automated design approaches. The standard cell library consists of logic gates, sequential elements, and macro cells implemented in a complementary fashion; along with bespoke circuits that exploit the unique properties of the relays. Architectures of a dual-wordline non-volatile memory and a mechanical flash analogue-to-
digital converter are proposed and implemented in the tooling flow, having been fabricated and electrically tested for proof of concept. Finally, all aspects of the work are brought together in the design of a temperature monitoring ASIC platform composed of roughly 600 mechanical switches.
| Date of Award | 7 May 2024 |
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| Original language | English |
| Awarding Institution |
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| Supervisor | I D B Pamunuwa (Supervisor) & Krishna Coimbatore Balram (Supervisor) |