Topology, Efficiency Analysis and Control of Four-level π-type Converters

  • Bosen Jin

Student thesis: Doctoral ThesisDoctor of Philosophy (PhD)

Abstract

The main focus of my PhD is to investigate and explore more efficient, reduced switching devices count four-level π-type converter topologies for low voltage applications (Vdc<600V). This thesis presents the work on four-level π-type converters during my PhD period. Average analytical mathematical models for analyzing the device power loss and the efficiency of the four-level π-type converter topology have been established. It has been found out that with the same input power level and the same dc input voltage, the four-level π-type converter can provide higher efficiency when switching frequencies are above 5 kHz compared to two-level and three-level converters due to lower switching losses. In order to resolve dc-link neutral points (NP) voltages unbalancing issues of neutral points clamped (NPC) multilevel converters, a carrier-based modulation (CB-PWM) NPs’ voltages balancing control with optimum zero-sequence signals injection for the four-level π-type converter has been investigated. Simulations and 300V dc input voltage experimental results proved that with a back-to-back configuration, the proposed control method is able to balance the three dc-link capacitors’ voltages even at high modulation indices and high-power-factor conditions. For the purpose to make the four-level π-type converter topology work as a single-end converter (inverter or rectifier) with balanced dc-link capacitors’ voltages, a modified topology based on the original four-level π-type converter has been developed and analyzed. This new topology is named as the hybrid-clamped four-level π-type converter with one more flying capacitor (FC) as well as two additional switching devices. With such layout modification, more redundant switching states can be generated to regulate neutral path currents. Therefore, the hybrid clamped four-level π-type converter does not have modulation index or power factor limitations when operating as a single-end converter.
Date of Award23 Jan 2020
Original languageEnglish
Awarding Institution
  • The University of Bristol
SupervisorPhil H Mellor (Supervisor) & Xibo Yuan (Supervisor)

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