Trigger design studies at future high-luminosity colliders

Student thesis: Doctoral ThesisDoctor of Philosophy (PhD)


The LHC will enter in 2026 its high-luminosity phase which will deliver a peak instantaneous luminosity of $7.5 \times 10^{34}$ cm$^{-2}$ s$^{-1}$ and produce events with an average pile-up of 200. In order to pursue its ambitious physics programme, the CMS experiment will undergo a major upgrade. The level-1 trigger will be replaced with a new system able to run the particle flow algorithm.
An algorithm that reconstructs jets and computes energy sums from particles found by the particle flow algorithm is presented in this thesis. The algorithm is able to provide similar performance to offline reconstruction and keep the same pt threshold as in the previous CMS runs.
The algorithm was implemented in firmware and tested on Xilinx FPGA. An agreement rate of 96% was obtained in a small-scale demonstrator setup running on a Xilinx FPGA. The full-scale algorithm is expected to use around 41.5% of LUTs, 11.6% of flip-flops, and 2.9% of DSPs of a Xilinx VU9P FPGA running at the frequency of 360~MHz.
The FCC-hh project studies the feasibility of a hadron collider operating at the centre-of-mass energy of 100 TeV after the LHC operations have ended. The collider is expected to operate at a base instantaneous luminosity of $5 \times 10^{34}$ cm$^{-2}$ s$^{-1}$, and reach a peak value of $30 \times 10^{34}$ cm$^{-2}$ s$^{-1}$ corresponding to an average pile-up of 200 and 1000, respectively.
Rates of a trigger system of a detector at FCC-hh were estimated by scaling rates of the Phase-2 CMS level-1 trigger and by developing a parameterised simulation of the Phase-1 trigger system. The results showed that at the instantaneous luminosity of $5 \times 10^{34}$ cm$^{-2}$ s$^{-1}$ the 100-kHz pt threshold is expected at 85 GeV, 170 GeV, and 350 GeV for single muon, e/gamma, and jet triggers, respectively.
Date of Award26 Nov 2020
Original languageEnglish
Awarding Institution
  • The University of Bristol
SupervisorJim J Brooke (Supervisor) & Joel Goldstein (Supervisor)


  • trigger
  • CMS
  • FCC
  • l1t
  • level-1 trigger
  • hardware
  • FPGA
  • HLS
  • LHC

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